1. Field of the Invention
The present invention relates to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) of a semiconductor circuit, and more particularly to a method for fabricating a MOSFET, capable of reducing the topology of a gate electrode of the MOSFET.
2. Description of the Prior Art
Generally, MOSFETs are employed in a semiconductor circuit. Such a MOSFET include a gate electrode formed on an active region of a semiconductor substrate and insulated from the semiconductor substrate, and a source and a drain respectively formed on opposite ends of the semiconductor substrate and having a junction structure. Conductors are in contact with the source and drain, respectively, so that the MOSFET is connected to other elements, thereby forming a circuit.
In a highly integrated semiconductor circuit, multilayered conductors are overlapped with the semiconductor substrate, thereby increasing the topology of the semiconductor circuit. Such an increase in topology results in an undesirable residue generated after patterning an upper layer deposited over the multilayer structure or formation of an inaccurate pattern.
A conventional method for fabricating a MOSFET having the general structure will be described in conjunction with FIG. 1.
In accordance with the method shown in FIG. 1, first, a mask is formed on a p type silicon substrate 1 so that a predetermined field region of the silicon substrate 1 is exposed through the mask. Using the mask, p.sup.+ type ions are implanted in the silicon substrate 1, thereby forming channel stopper regions 2. Thereafter, a field oxide film 3 is formed on the silicon substrate 1. On a portion of the silicon substrate 1 corresponding to an active region, a gate oxide film 4 and a gate electrode 5 comprised of a polysilicon film are then formed. Subsequently, N.sup.- type ions are implanted in the silicon substrate 1. After the implantation of N.sup.- type ions, insulating film spacers 6 are formed on side walls of the gate electrode 5, respectively. N.sup.+ type ions are then implanted in the silicon substrate 1, thereby forming a source 7A and a drain 7B. Over the entire exposed surface of the resulting structure, an interlayer insulating film 8 are formed. The interlayer insulating film 8 is then subjected to an etch so as to form contact holes 9 through which the source 7A and the drain 7B are exposed, respectively. Finally, a metal wiring 10 being in contact with the source 7A and the drain 7B is formed on the resulting structure.
In accordance with the conventional method, however, an increase in topology occurs because the gate electrode is protruded from the upper surface of the silicon substrate. As a result, the conventional method encounters a problem of an addition of a planarization process step required upon forming the upper layer. The conventional method also involves a problem of a spiking phenomenon occurring at the surface of the substrate because the metal wiring is in direct contact with the source and the drain.